1. Field of the Invention
The present invention relates to a semiconductor device, and particularly, to a semiconductor device and a method of fabricating the same to form a metal silicide layer having a stable resistance characteristic by compensating for a loss of silicon.
2. Description of the Related Art
In general, as a semiconductor device becomes geometrically smaller, gate, source and drain regions are decreasing in size, and a junction between the source region and the drain region needs to be shallower. However, for these reasons, high-resistance regions are undesirably generated.
Accordingly, to reduce the resistance between the source and drain regions and a polycrystalline silicon region, a high melting point metal silicide is used on contacts between those regions.
Whenever contacts between the source and drain regions and the exposed silicon occur during processes, a thin film of high melting point metal is deposited and heated to form a silicide. In this process, various silicide compounds including platinum, manganese, cobalt, titan, or the like are used.
A method of fabricating a related art semiconductor device will now be described referring to accompanying drawings.
FIGS. 1A to 1F are cross-sectional views illustrating a method of fabricating the related art semiconductor device.
As shown in FIG. 1A, a semiconductor substrate 21 includes active regions and device isolation regions, and device isolation layers 22 are formed in the device isolation regions through a local oxidation of silicon (LOCOS) or shallow trench isolation (STI) process.
Then, the semiconductor substrate 21 is thermally oxidized at a high temperature to form a gate oxidation layer 23 on the semiconductor substrate 21.
As shown in FIG. 1B, n-type or p-type impurity ions for forming a channel of a transistor are selectively implanted in the active region of the semiconductor substrate 21 to form an n-well or p-well (not shown), and a thermal process is performed thereon at a high temperature of about 1050˜1200° C.
Then, a polysilicon layer is deposited on the gate oxidation layer 23, and the polysilicon layer and the gate oxidation layer 23 are selectively etched through a photolithography process, to form a gate electrode 24.
N-type impurity ions or p-type impurity ions are implanted to an entire surface of the semiconductor substrate 21, using the gate electrode 24 as a mask, to form lightly doped drain (LDD) regions 25 in surface portions of the semiconductor substrate 21 that are located at both sides of the gate electrode 24, respectively.
As shown in FIG. 1C, an insulating layer is deposited on an entire surface of the semiconductor substrate 21 by a low pressure chemical vapor deposition (LPCVP) method, and then an etch-back process is performed on the entire surface thereof to form insulating layer sidewalls 26 at both sides of the gate electrode 24.
Then, n-type or p-type high-concentration impurity ions are implanted to the entire surface of the semiconductor substrate 21 using the gate electrode 24 and the insulating layer sidewalls 26 as a mask, to form source-drain impurity regions 27 in surface portions of the semiconductor substrate 21 that are located, respectively, at both sides of the gate electrode 24, and then a thermal process is performed thereon at a temperature of about 1000˜1050° C.
As shown in FIG. 1D, a washing process is performed to remove from the semiconductor substrate 21 various target materials such as metal impurities, organic contaminants, natural oxidation layer.
Then, the semiconductor substrate 21 having passed through the washing process is transferred to a sputter chamber (not shown) of sputtering equipment, and a nickel layer 28 is formed on the entire surface of the semiconductor substrate 21 by sputtering.
As shown in FIG. 1E, the semiconductor substrate 21 is provided into rapid thermal process (RTP) equipment or an electric furnace and is thermally processed at a temperature of 400˜600° C., to form a nickel silicide layer 29 on the surface of the semiconductor substrate 21 including the gate electrode 24 and the source and drain impurity regions 27.
Specifically, during the thermal process, silicon ions of the gate electrode 24 and the semiconductor substrate 21 react with nickel ions of the nickel layer 28, thereby forming the nickel silicide layer 29. However, such a reaction does not occur in the insulating layer sidewalls 26 and the device isolation layers 22, and thus the nickel layer 28 still remains thereon.
As shown in FIG. 1F, the remaining nickel layer 28 that does not participate in the formation of the nickel silicide layer 29 is removed, and then the semiconductor substrate 21 is annealed at a predetermined temperature to stabilize a phase of the nickel silicide layer 29, thereby completing a low-resistance nickel silicide layer 29.
However, the related art method of fabricating a semiconductor device has the following problems.
Because nickel silicide (NiSi) is formed. within such a narrow temperature range, temperature deviation from the temperature range by only about 10° C. causes a material such as Ni2Si or NiSi2 that has high resistance to be generated.
Therefore, a nickel silicide (NiSi) needs to be formed even at a low temperature.